Massive MIMO (multiple-input multiple-output) is a key 5G (5th Generation) mobile communication technology recognized in the industry, and significantly improves spectral efficiency by using massive antennas. Because a future 5G system requires a low latency, high energy efficiency, high cost efficiency, and high spectral efficiency, if the massive MIMO uses a conventional precoding architecture in which precoding is implemented on a baseband and a quantity of intermediate radio frequency channels is the same as a quantity of transmit antennas, there may be very high baseband processing complexity and very high complexity and costs of intermediate radio frequency implementation. To resolve this problem, two-stage precoding becomes a research focus of the massive MIMO. Spatial dimension reduction is implemented by performing stage-1 precoding on an intermediate radio frequency, reducing complexity and costs, and a baseband performs stage-2 precoding to implement multi-user interference suppression. Most of existing two-stage precoding studies are focused on a system in which uplink-downlink channel reciprocity can be applied, for example, an LTE (long term evolution) TDD (time division duplex) system, where downlink channel information is estimated and obtained by using an uplink pilot signal. However, for a system in which an uplink and a downlink are in different frequency bands, for example, an LTE FDD (frequency division duplex) system, currently there is a lack of two-stage precoding solution, especially a channel information feedback solution in the two-stage precoding solution, that can be applied to a DBF (digital precoding or digital beamforming) hardware architecture or a fully connected two-stage HBF (hybrid analog and digital precoding or hybrid analog and digital beamforming) hardware architecture and that provides performance satisfying a system requirement. Therefore, there is a need for a two-stage precoding solution that includes a channel information feedback solution and provides relatively good performance when being applied to the DBF hardware architecture or the fully connected two-stage HBF hardware architecture.